There are many known techniques for lowering the effective dielectric constant for the dielectrics used in semiconductor devices, however most of these methods suffer from several drawbacks including poor mechanical strength. This poor mechanical strength results in reliability issues in the final device.
For example, one methodology for creating insulator voids (gaps, airgaps, etc.) in dielectric materials embedded in multilevel integrated interconnect structures to lower the effective dielectric constant includes the combination of supra-lithographic plus sub-lithographic masking to create selectively blocked-out nanocolumns or airgaps in an already-built wiring level as disclosed in US2005/0167838A1. The method includes at least one layer of a block out mask and a layer of diblock copolymer which forms tiny self assembled perforations (200A) in a polymeric matrix which are then transferred into the underlying dielectric to create a nanocolumnar structure. Further, ways to isotropically increase column or gap size underneath a perforated mask, such that larger gaps could be made without impacting rapid pinch off are described. However, problems exist with this method. For example, it is not readily practicable for larger dimension copper wiring levels. When supra-lithographic block out shapes are combined with a self assembled layer to create a sublithographic nanocolumnar structure, significant areas of the copper interconnect surfaces are exposed to etch, strip, and wet clean processes through the nano-sized perforated perforations in the cap. Although these perforations may be plugged by the subsequent pinchoff deposition of an additional cap dielectric material, there may be excessive copper sputtered through the perforations, and possibly integration defects associated with these copper and copper/cap interface exposures. Another potential problem is scaling to very large dimension wiring levels due to increased aspect ratios for nanocolumn etching, assuming the sublithographic mask perforations could not be scaled accordingly. Finally, such method requires two cycles of mask apply, develop, and reactive ion etching for the diblock and blockout pattern transfer.
A different method for forming an airgap is described in US 2006/0183315 (Ser. No. 10/906,267) using electron-beam and UV radiation to selectively damage the SiCOH interlayer dielectric. A blockout mask limits exposure to the electron-beam or UV such that only the areas not covered by the blockout mask get exposed to the radiation with the result that the exposed regions of the dielectric are demethylated and are thus rendered etchable. However, the main drawback of this method is that the depth and extent to which the UV or the electron-beam demethylates damages the SiCOH dielectric and the damaged dielectric may extend all the way to the depth of the trench.
An etchback process is disclosed in Integration of a 3 Level Cu—SiO2 Air Gap Interconnect for Sub 0.1 micron CMOS Technologies (2001 Proc. IEEE International Interconnect Technology Conference, 2001, pages 298-300, Arnal et al.) wherein a full trench is etched through a lithographic mask into the underlying dielectric. A pinch-off airgap is then formed during the deposition of the next level of dielectric. This method has several drawbacks including problems of excess topography in the next level after dielectric deposition which requires added chemically-mechanically polished touchup or changes to the interlayer dielectric process as well as excess redeposition in airgaps, and in the extreme, pinch-off points which are so high that they can interfere with trenches on the subsequent wiring level. Additionally, in this method, there will be situations where there are several levels of dielectric and pinch-off airgap that can be stacked on top of each other without any intervening compressive film to break up the buildup of tensile stress with the result that this structure is mechanically unstable. Finally, this method does not scale well with shrinking dimensions and airgaps at the thin wire level using aggressive shrink factors and cannot easily be fabricated using it due to the fact that there will be exposed copper along the entire length of an interconnect during the etchback resulting in electromigration failures during reliability stressing.
Thus there exists a need for an airgap method which limits exposed copper during etching and in some cases eliminates it. A further need exists for an airgap method where pinch-off heights are limited such that the trench bottoms from the subsequent level do not intersect the pinch-off gaps.
There further exists a need for an airgap structure where there is no build-up of topography after the subsequent level dielectric deposition. Another need exists for an airgap structure where there is no build-up of tensile dielectric or airgap without compressive films to interrupt the build up of the gaps and tensile stress areas. There further exists a need for an airgap method where the depth of the gap is not limited by limitations of etch due to high aspect ratios.
A need further exists for an airgap method where the depth of the gap is not limited by the depth to which the dielectric can be demethylated and thus rendered etchable. Additionally, a need exists for a streamlined airgap method with less masking and etching steps per wiring level while still ensuring that the gaps can be made at thin wire levels which are close to the transistor as well as “fat” wires which reside at the upper levels of the interconnect scheme in a hierarchical structure.
These needs and many others are met by a process for producing airgaps on a substrate using the inventive method which uses a self aligned template with sub and supra lithographic perforations within a blockout mask. Other advantages of the present invention will become apparent from the following description and appended claims.